Zalt: System overview

I have been writing about the components that make up the Zalt Z80 computer. I realize that it may be overwhelming and hard to follow how the components interact. That is why I made a block diagram of what the Zalt computer components are at this time. Being that Zalt is built as a modular system (an attempt anyway) more components can be added at a later time.

Here is the block diagram:

Diagrams

The squares are the components that make up the Zalt computer. We’ll talk about each component in a little more details. The thick lines between the components are the buses. The address bus (light blue), the data bus (green) and the control bus (red) that contains all the typical Z80 control lines like, MEMREQ, IOREQ, RD and WR etc. Thinner lines are sub-sets of the bus signals or dedicated signals.

CPU

This is the Z80 CPU that is located on the CPU board. All address and data bus lines are connected to their buses as well as all the control lines. The clock (not drawn) is generated by the SysCtrl component. Interrupt signals INT and NMI are not used at this time and pulled high (inactive).

RAM

The RAM component currently consists of 4 static RAM chips of 64k (8 bits) each, located on the CPU board. These chips are enabled by the Logic component whenever it detects a valid Memory Address range. The address lines A0-A11 are connected to the address bus lines A0-A11. The RAM’s A12-A15 are connected to the Memory Address lines MA12-MA15 (also in the address bus). Because the design allows for a bank-switched memory layout all memory has to be connected the (upper) Memory Addres lines (MA12-MA19). In total we have 20 Memory Address lines (A0-A11 and MA12-MA19) that allows a total memory of 1MB. The RAM’s data lines are connected to the data bus.

SysCtrl

The System Controller component is a PSoC5 module, currently  located on the Bus-Spy board. It is actually a dev-kit for the PSoC5 but at $10.= it is a very economical choice. Because the Zalt computer does not have an ROM, the System Controller is responsible for booting the computer. It has a serial connection with the PC and implements several commands that allow the user to upload the program and execute it.

The System Controller also monitors the control bus to see if there is an IO-request ($0000-$00FF). Currently it implements IO address $20 (hex) to connect the Z80 program to the serial link to the PC. That means that the Z80 program can print characters on the PC screen (running a terminal program) and receive keyboard input.

The System Controller is also the source of the system clock. It implements commands to change the speed of the system clock, which is convenient for debugging.

MMU

The Memory Management Unit component is also located on the CPU board. It is hardware (4 ICs) that is in charge of mapping the upper address lines A12-A15 to Memory Addresses MA12-MA19. It does this by storing the memory map in a 32k fast (15ns) static RAM. The address lines A12-A15 address the memory map RAM (A0-A3) and the data stored at these locations is output as MA12-MA19 (8 bits).

The MMU component receives control signals from the Logic component that decodes if the program (or System Controller) tries to write or read the memory map. This allows the program (or the System Controller) to initialize and later change the contents of the memory map table by issuing output instructions on the correct IO-address ($F8F0-$FFFF).

Logic

The Logic component is an Altera Max II CPLD (EPM240) IC. This programmable logic IC contains the logic for decoding the IO addresses for interacting with the MMU component as well the decoding for enabling the correct RAM chips during a memory-request. All address bus and control bus signals are fed into the chip. The data bus is not connected.

Currently less than 10% is used of its capacity for the logic contains only combinatoric logic expressions, which are pretty cheap. There are more than 30 free IO pins left on the CPLD chip for future use.

Wrap-up

Well, there you have it. I hope it sheds some light on the organization of the Zalt system components. The only thing not covered in the overview is the Bus-Spy board that houses the System Controller. The Bus-Spy is connected to all address and data lines and uses a couple of control signals to generate strobe and latch signals for displaying purposes.

Published in: on June 29, 2016 at 8:26 am  Leave a Comment  

Zalt: The Decoder Board (again)

After I had finished my hand-wired Bus-Spy board, I turned my attention to the Decoder board. I had already assembled the Decoder board PCB with the clamp diodes and resistors I needed to bring the 5V signals down to 3V3 and visa versa. There is documentation on the Altera site on how to do this.

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This is the Decoder board as it came from Elecrow. This time I opted for the green solder mask just to see what the quality would be. Again, Elecrow has delivered excellent work, although this time, on few via’s, the hole was a little off center. No break outs or anything, so not a problem.

I had already ordered all the passive SMD diodes, resistors and capacitors that needed to go on the board. After a few hours soldering with my magnifier (old eyes) it looked like this.

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As you can see, I did not populate everything just yet, although I did solder all the diodes. This is because of the 80 IO pins the Altera Max II (EPM240) has, I only needed about two-thirds. The rest is will be done as needed. For the unconnected IO pins I designed both a pull-up resistor for output as well as a series resistor for input. Because I did not solder the resistors for the unconnected pins, those pins are physically isolated from the header pins they connect to.

After I had the Bus-Spy board and the CPU board running, I could do DMA from the System Controller (on the Bus-Spy board) and run a simple ‘Hello World’ program from RAM I added the Decoder board to the stack. Without the Decoder board, I had to use a jump wire to connect the enable for the RAM chip to the Z80 MEMREQ control line in order for it to work – otherwise the (one and only) memory chip would never be enabled.

In order to start small and test if the Max II could even be programmed I coded the following VHDL:

MBE0 <= MEMREQ;

Sheer brilliance if you ask me. Basically the jump wire in code: let the first (zero) Memory Bank Enable be the same as the Z80 MEMREQ.

I was pleasantly surprised when the Quartus software programmed my board on the first try and my simple “Hello World” test program ran once again. That meant that the Decoder board was basically working! Whoohoo!

The tower of power was growing:

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Published in: on June 26, 2016 at 7:14 am  Leave a Comment  

Zalt: Working on the Bus-Spy board

It has been a while since I wrote about my home brew Z80 computer project now called Zalt. It is not that I haven’t made any progress – although at times it has been slow- I just did not write it down. So here is what happened.

After designing the Decoder board PCB and having it manufactured I thought making the Bus-Spy board would be a good pass time project while I was waiting for the Decoder board to show up in my mailbox.

The Bus-Spy board I ended up making, houses the System Controller (the Cypress PSoC5), some logic to drive 8 TIL311’s my pen-friend Ron was kind enough to sent me -and a duplication of the bus connectors to make it easy to hook on extra logic or the logic analyzer for debugging.

I decided to make this board by hand and used 30AWG wirewrap wire to do the connections. It was a little more work than I thought, although I have made these type of boards before, so I did not get it finished before my Decoder board showed up. But I decided to focus on the Bus-Spy board because that would allow me to do away with all the bread boards and temporary wire-mess.

When it was time to test it, I discovered that the 100mA current a TIL311 may draw on average is a little much for 30AWG wire and I had a considerable voltage drop across my power lines from my poor-man’s bench supply: an old 300W PC supply. So much so that I only had 4.4V on some of the IC’s on the CPU board. I dug in the parts bin for a beefier wire, put on some banana plugs on one side and soldered a connector to the other. I then routed the power directly from that connection on the Bus-Spy board to the TIL311’s supply pins with some thicker wire. That fixed it.

There was one goof-up I only discovered when I was staring at the TIL311’s. I had reversed the order of the LSB/MSB on the displays. I can’t believe I didn’t notice that earlier! Doh!

So from left to right, the first digit is A0-3, the 2nd A4-7 etc. instead of the other way around. Ah, well. I printed out a small piece of paper indicating what each digit is. If/when I create a real PCB for the bus-spy, I will make sure this is fixed.

 

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This photo was taken before I fixed the power.

I used the two decimal points on the TILL311’s to indicate the status of some of the control lines (as you can see on the legend I printed out).

The top (left) IC is a GAL16V8 that is programmed to deliver the Strobe signal for the TIL311’s and the Load signal for the two 74-573’s that latch the control signals. There is a row of jumpers (just above the displays on the left) that tell the GAL16V8 what events to capture. This allows you for instance to concentrate on just memory-writes or instruction cycles (M1) etc. Each jumper turns on a specific event type. Removing the jumper turns it off.

You’ll notice that the size of this board is a standard eurocard size (10cm x 15cm). That means that the other boards can go on top and you’ll still be able to see the display digits.

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Here I am performing a basic DMA test where the System Controller on the Bus-Spy board talks to the Memory on the CPU board. I have removed all other ICs to keep it simple.

That is when I discovered that I had a problem. The values I wrote to the memory were not read back correctly. After some digging I found that I had not seated the IDC flat-cable connectors properly. The middle wires were making intermittent contact. So after pressing them down firmly in the vice, it all started working. You’ll be amazed at how much force you need to press down 40 pins into the wires of the flat-cable…

With this out of the way, I could focus on the Decoder board.

Published in: on June 25, 2016 at 6:13 am  Leave a Comment  

Retro Z80 is now Zalt

Previously I have headed my blog posts with ‘Retro Z80’ to indicate my Z80 computer project.

Although the Z80 part is correct and can be considered retro, the rest of my project is not so retro. I use a Cypress PSoC 5 as a System Controller that is an ARM processor and a CPLD/FPGA combined. I also use the Altera Max II (EPM240) CPLD. Both these devices are hardly retro, not the latest greatest – bleeding edge, but certainly not retro – at least not in the next few years.

So when I was creating a target for the z88dk I had to come up with a name. It was at that time that I choose Zalt. Obviously it sounds like salt. Sweet short and a little different.

The Z in Zalt refers to the Z80 CPU. The ‘alt’ in Zalt is for alternative. Because I am not sticking to true retro components I thought this was very appropriate.

So from now on, my blog posts about my Z80 computer project will be headed with Zalt instead of Retro Z80.

 

Published in: on June 24, 2016 at 5:04 pm  Leave a Comment