Zalt: System overview

I have been writing about the components that make up the Zalt Z80 computer. I realize that it may be overwhelming and hard to follow how the components interact. That is why I made a block diagram of what the Zalt computer components are at this time. Being that Zalt is built as a modular system (an attempt anyway) more components can be added at a later time.

Here is the block diagram:

Diagrams

The squares are the components that make up the Zalt computer. We’ll talk about each component in a little more details. The thick lines between the components are the buses. The address bus (light blue), the data bus (green) and the control bus (red) that contains all the typical Z80 control lines like, MEMREQ, IOREQ, RD and WR etc. Thinner lines are sub-sets of the bus signals or dedicated signals.

CPU

This is the Z80 CPU that is located on the CPU board. All address and data bus lines are connected to their buses as well as all the control lines. The clock (not drawn) is generated by the SysCtrl component. Interrupt signals INT and NMI are not used at this time and pulled high (inactive).

RAM

The RAM component currently consists of 4 static RAM chips of 64k (8 bits) each, located on the CPU board. These chips are enabled by the Logic component whenever it detects a valid Memory Address range. The address lines A0-A11 are connected to the address bus lines A0-A11. The RAM’s A12-A15 are connected to the Memory Address lines MA12-MA15 (also in the address bus). Because the design allows for a bank-switched memory layout all memory has to be connected the (upper) Memory Addres lines (MA12-MA19). In total we have 20 Memory Address lines (A0-A11 and MA12-MA19) that allows a total memory of 1MB. The RAM’s data lines are connected to the data bus.

SysCtrl

The System Controller component is a PSoC5 module, currently  located on the Bus-Spy board. It is actually a dev-kit for the PSoC5 but at $10.= it is a very economical choice. Because the Zalt computer does not have an ROM, the System Controller is responsible for booting the computer. It has a serial connection with the PC and implements several commands that allow the user to upload the program and execute it.

The System Controller also monitors the control bus to see if there is an IO-request ($0000-$00FF). Currently it implements IO address $20 (hex) to connect the Z80 program to the serial link to the PC. That means that the Z80 program can print characters on the PC screen (running a terminal program) and receive keyboard input.

The System Controller is also the source of the system clock. It implements commands to change the speed of the system clock, which is convenient for debugging.

MMU

The Memory Management Unit component is also located on the CPU board. It is hardware (4 ICs) that is in charge of mapping the upper address lines A12-A15 to Memory Addresses MA12-MA19. It does this by storing the memory map in a 32k fast (15ns) static RAM. The address lines A12-A15 address the memory map RAM (A0-A3) and the data stored at these locations is output as MA12-MA19 (8 bits).

The MMU component receives control signals from the Logic component that decodes if the program (or System Controller) tries to write or read the memory map. This allows the program (or the System Controller) to initialize and later change the contents of the memory map table by issuing output instructions on the correct IO-address ($F8F0-$FFFF).

Logic

The Logic component is an Altera Max II CPLD (EPM240) IC. This programmable logic IC contains the logic for decoding the IO addresses for interacting with the MMU component as well the decoding for enabling the correct RAM chips during a memory-request. All address bus and control bus signals are fed into the chip. The data bus is not connected.

Currently less than 10% is used of its capacity for the logic contains only combinatoric logic expressions, which are pretty cheap. There are more than 30 free IO pins left on the CPLD chip for future use.

Wrap-up

Well, there you have it. I hope it sheds some light on the organization of the Zalt system components. The only thing not covered in the overview is the Bus-Spy board that houses the System Controller. The Bus-Spy is connected to all address and data lines and uses a couple of control signals to generate strobe and latch signals for displaying purposes.

Advertisements
Published in: on June 29, 2016 at 8:26 am  Leave a Comment  

The URI to TrackBack this entry is: https://jacobielectronix.wordpress.com/2016/06/29/zalt-system-overview/trackback/

RSS feed for comments on this post.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s

%d bloggers like this: